1. Field of Invention
Methods consistent with the present invention relate to a stacked die semiconductor package. More particularly, the method relates to through-silicon vias (TSV) interconnect 3-D packages. The method uses wafers that have been processed (i.e., blind etched, back grinded, laminated with bond material at underside, etc) to form the stacked a structure.
2. Background and Description of the Related Art
The relatively new through-silicon vias, or TSV, technique involves stacking chips vertically in a package and then creating connections between the bottom of the top chip and the top of the bottom chip. Major challenges in TSV interconnect 3-D packaging include: (1) how to handle thin wafers; (2) new equipment to handle wafer level operations; and (3) testing TSV wafers. Other concerns include reliability and “void” and “pop-corn” issues, which typically arise due to vapor trapped within the package. In addition, each wafer of the stack is subjected to a plating process which is long and time consuming, which hampers production capacity.
Conventional TSV packages are handled using expensive wafer handling equipment with temporary carrier bonding. Identifying a bonding material that can withstand high temperature metal deposition processes is another major challenge. De-bonding is another high risk process which can damage the wafer, which has already undergone all the front end operations.
One convention TSV method is disclosed in U.S. Pat. No. 7,276,799. The chip stack package in this patent is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. However, this method may create reliability issues resulting from inadequate contact between bond pad, the conductive coating and the solder material within the apertures.
There is therefore a need to provide a method that can prevent or at least ameliorate on or more of the disadvantages of the prior art. One objective of the present invention is to have a simpler assembly process that leads to a better interconnect reliability package. The package will also have better electrical and mechanical performance.